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Keywords
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CMOS DC‐DC buck converter, compact, complement value leaping (CVL), PWM technique, ultralow power
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Abstract
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A very compact ultra‐low power DC‐DC buck converter is presented. The proposed buck converter employs a novel complement value leaping pulsewidth modulation (PWM) technique to realize the desired DC mean‐value for various loads. Incorporating just two counters with a simple digital controller to load the repeatedly complemented value of the 4bit up/down counter as the initial value of the least significant bits of the 5bit up counter, a PWM pulse is created to manage the charge/recharge period. The realized PWM signal maintains the same desired output voltage mean value for any load resistance between 80 and 140 Ω. The switching frequency is 160 kHz, and the overall power consumption is 26.9 nW, while the efficiency is 93.4% for current range of 1.7 to 3 mA. The performance of the proposed converter is validated by Cadence post‐layout simulations utilizing TSMC180nm CMOS technology for 1‐V supply voltage providing the output voltage mean value of 0.24 V.
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