Research Specifications

In this paper, a novel versatile calibration technique is proposed for current-steering binary-weighted DACs. This work is motivated by the fact that, in spite of the relative tendency to utilize the binary-weighted converters, there are very few calibration techniques dealing with their matching accuracy and transient performance. The introduced calibration technique can dynamically calibrate the DAC, in an arbitrary and repeated manner whenever needed. The system utilizes two clock pulses: the slow one for calibration and the other high-speed pulse for normal operation. The proposed calibration structure can strictly eliminate transistor mismatch-induced errors incorporating a unique calibration block utilized in an algorithmic manner for all current blocks. Implementing a configurable triple-path scheme, the current reference is updated by summing all of the adjusted LSB currents up, to calibrate the next upper MSB current. The transient behavior is improved due to the built-in intrinsic positive feedback-enabled deglitcher. Introducing tremendous overall current error as high as 125 LSB to the binary current blocks, the performance of the proposed calibration technique is validated for a 10-bit DAC by Cadence simulations utilizing TSMC 180-nm CMOS technology applying sampling frequency of 125 MHz for 1.8 V supply voltage and 500 nA LSB current.