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Abstract
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In this paper, the structure of a 16-by-16 unsigned hybrid (serial-parallel) multiplier has been proposed. Parallel multipliers, in-comparison with serial multipliers,have higher speed and higher power consumption. In hybrid structures, to reduce power and increase speed,both serial and parallel techniques are used. The proposed structure improves propagation delay and reduces power consumption using pipeline and retime techniques. Simulation results show that it has 5.7 ns propagation delay and 2.65 mW power consumption. The figure of merit for energy consumption is 15.2 PJ. The proposed multiplier has been designed using 0.18 μm TSMC process at 1.8 V supply and simulated using Cadence tools. The layout of the multiplier occupies 52414 μm2.
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